Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
FIG. 1 illustrates a schematic diagram of a portion of a typical prior art NAND architecture memory array comprising series strings of non-volatile memory cells. The array is comprised of an array of non-volatile memory cells 101 (e.g., floating gate) arranged in series strings 104, 105 that are referred to as columns. Each of the cells 101 are coupled drain to source in each series string 104, 105. A select line, such as word lines WL0-WL31, that spans across multiple series strings 104, 105 is coupled to the control gates of each memory cell to form what is conventionally referred to as a row in order to control their operation in response to biasing of the bit lines. Transfer lines, such as the bit lines BL1, BL2 are coupled to sense amplifiers (not shown) that detect the state of each cell by sensing current on a particular bit line.
The word lines WL0-WL31 select the individual memory cells in the series strings 104, 105 to be written to or read from and operate the remaining memory cells in each series string 104, 105 in a pass through mode. Each series string 104, 105 of memory cells is coupled to a source line 106 by a source select gate 116, 117 and to an individual bit line BL1, BL2 by a drain select gate 112, 113. The source select gates 116, 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates 112, 113 are controlled by a drain select gate control line SG(D) 114.
Each memory cell can be programmed as a single level cell (SLC) or multilevel cell (MLC). Each cell's threshold voltage (Vt) is indicative of the data that is stored in the cell. For example, in an SLC, a Vt of 0.5V might indicate a programmed cell while a Vt of −0.5V might indicate an erased cell. The MLC may have multiple Vt windows (i.e., a range of Vt voltages) that each indicate a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.
The resistance of a series string of memory cells varies in response to the programmed pattern of the memory cells above a target cell in the series string. A change in resistance causes the bit line discharge rate to change, resulting in the appearance of a higher threshold voltage for a read cell.
FIG. 2 illustrates a schematic diagram of an equivalent circuit representing one of the NAND memory cell strings in accordance with FIG. 1. The equivalent circuit is comprised of the bit line 201 that is coupled to the memory cell series string equivalent 200. The string equivalent 200 is comprised of a select gate drain transistor 204 that couples the string to the bit line 201. A select gate source transistor 205 couples the string 200 to the source line 202. A target memory cell 209 is the memory cell of the string that is selected to be programmed or read. In the illustrated embodiment, the target transistor 209 is at the bottom of the string 200 closest to the source line 202.
A resistance 207 represents the sum, Rs, of all of the resistances of the memory cells in the NAND string 200 between the target memory cell 209 and the select gate drain transistor 204 (i.e., above the selected cell). The capacitance 208 represents the total capacitance of the memory cells of the NAND string 200 above the target memory cell 209.
In a typical prior art sensing operation, the series string of memory cells is initially precharged from the bit line 201 to which it is coupled. An attempt is then made to discharge the series string current through the target cell to be read/verified. If the target cell is erased, the string discharges. If the cell is programmed, the string does not discharge. This scheme is used to determine the programmed state of a target cell.
When writing to the target cell 209, all of the memory cells in the string above it are normally erased since programming of a memory string typically begins at the bottom cell. In this case, Rs is small resulting in a higher bit line current during the verify operation.
In a worst case scenario, all of the cells in the string 200 above the target cell 209 are then programmed, thus increasing Rs. With an increased Rs, the bit line current decreases and a read operation of the target cell 209 might appear to have a threshold voltage that is outside of the programmed state. In any case, the increase of the resistance of the series string of memory cells when programmed will add a certain level of millivolts that opens the Vt distribution window and makes it appear that the read cell has a higher threshold voltage than what was programmed. Since the series resistance varies due to the different, unknown states of the cells above the selected cell, the amount of change in Vt cannot be predicted.
For the reasons stated above and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for compensation of this back pattern effect in a memory device.